LTspice - simulation error

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Joined: Sun Feb 09, 2014 2:30 pm

LTspice - simulation error

Post by gibrocksonne »


I was simulating a H-bridge with LTspice mosfet, it was working fine. I added a new NMOS from ST (STF10N60M2), ST provides 2 models :

- V2 : simulation speed is very slow and abort after 1-2% : "Analysys: time step too small; time = ..., timestep=1.25e-19:trouble with node u1.d"

- V3 : simulation does not start, "port(pin) count mismatch between the definition of subcircuit "stf10n60m2_v3" and instance "xu1""

Any ideas?
Thank you:)
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Post by Ray »

If you would post your schematic and the SPICE models you are trying to use someone might be able to help.

Having said that, it's important to make sure that the symbols you use in your LTspice schematic match the device models you have. From your description, here is what I think is going on.

First, the two SPICE models you have for the STF10N60M2 are for two configurations: (1) a three-terminal device with the substrate internally connected to the source; and (2) a four-terminal device with the substrate brought out to a separate pin. Since your simulation reports a pin mismatch when using the V3 model, I suspect that your schematic calls for the three-terminal device. So you should use the V2 model.

Second, the internal LTspice NMOS symbols assume that your device is modeled using the generic NMOS model, using the ".MODEL" statement. The SPICE models you got from the STMicroelectronics website are likely subcircuits. These are incompatible with the built-in LTspice NMOS symbols. The solution is to create new symbols that expect a device defined as a subcircuit instead of model. The easiest way to do this is to open the symbol file with a text editor, change the "SYMATTR Prefix" to X, and save the symbol to a new file with an "x" prefix. I've done this for you; the new symbols are attached (xnmos.asy and xnmos4.asy).

To fix your problem, I think you will need to use the xnmos.asy symbol with the V2 model file.

I hope this helps.
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